This invention relates to a semiconductor memory device, and more particularly, to a device permitting data readout operation at high speed.
A method of accessing data in an ordinary DRAM will be first described with reference to FIG. 10 in which the configuration of the memory cell periphery is shown. Memory cells as a memory cell array are arranged in a matrix manner. One memory cell is of a structure including a pair of a charge hold capacitor Cla and a charge transfer transistor Tla connected to one sense amplifier 101 by a bit line pair 301a and 301b, respectively. Selection of each memory cell is made by the row address and the column address. The row address is the address relating to selection of word lines 201, 202, . . . connected to the transfer transistor, and the column address is the address relating to the selection of I/0 transfer gates Gl, . . . , Gm connected to sense amplifiers 101, . . . , 10m to function as switch circuits, respectively.
In such a DRAM, in reading out data held in any memory cell, an approach is employed to first select any one of word lines 201, 202, . . . by the address to raise a potential thereon to transfer data of a memory cell connected to that word line to any one of bit line pairs 301a, 301b, . . . 30ma, 30mb. Data thus transferred is amplified by any one of sense amplifiers 101, . . . , 10m, thus allowing potentials on respective bit line pairs 301a, 301b, . . . 30ma, 30mb to be equal to a potential difference corresponding to data stored in the connected memory cell. Then, any one of I/0 transfer gates Gl, . . . , Gm connected to the memory cell to be read out is selected by a column address. Thus, data of one bit line pair is outputted from the I/O line.
Data has been read out in the prior art in this way. The ratio of the time until sense of a bit line is completed after the row address is established to the time when the column address is required takes a considerably large value of 1/2 to 2/3 of the entire access time. For example, in the case of DRAM having the entire access time of 80 ns, it takes 40 to 50 ns for sensing the bit line. This constitutes an obstacle to high speed. In this case, since the row address and the column address have a time difference therebetween at a necessary timing, DRAM adopts a multiplex system of taking both addresses from a shared address pin thereinto.
In accordance with this system, the readout of data is divided into the portion corresponding to the row address and the portion corresponding to the column address. For this reason, in the access cycle where the row address does not change with respect to that in the last cycle, but only the column address changes, data of a memory cell connected to the same word line in the last cycle is already sensed. Thus, by immediately selecting an I/O transfer gate by the column address, the access time can be shortened. This system can read out data in a time one half to one third than that in the case of sensing data for a second time.
However, in the case of the multiplex system, since the control method becomes complicated, this system is not suitable for small scale systems. An address system similar to that in SRAM is demanded. To cope with such a demand, PSRAM (Pseudo Static RAM) has been newly used in medium and small scale computer systems in recent years. Such PSRAM is not based on the multiplex system as in DRAMs, but is based on a system similar to that in SRAM to give the row address and the column address at the same time, to thus generate timings used in respective circuits in the chip. This advantageously provides the following merits: A control signal for fetching a column address (CAS signal) required for the multiplex system becomes unnecessary; the control circuit is not more complicated than that in DRAM; the cost per bit is lower than that of SRAM.
The readout operation of a certain kind of such a PSRAM will be described in conjunction with the timing chart of respective signals of FIG. 11. When the chip enable signal (CE signal) is at high (H) level, the bit line is equalized and precharged. Further, the word line is placed in a reset precharge state. At time t1 when the CE signal falls from H level to low (L) level, an address is fetched. Thus, an access of data is initiated. In this example, a row address is fetched at the fall time tl of the CE signal. The time for maintaining this signal level varies depending upon the kind of the address latch systems. In the case of latch, it is sufficient to maintain this level until t2. With respect to the dotted portions subsequent thereto, in the case where no latch operation is performed, it is necessary to maintain the level irrespective of what level is until t4. With respect to the hatched portions subsequent to t4, it is unnecessary to hold the signal level in any event. Thus, the row address is held until the rise time t3 of the CE signal. On the other hand, the level change of the column address is detected by the transition detector for detecting changes in the signal level. Thus, selection of I/O transfer gate is carried out, and data is read out.
At this time, where the row address and the column address are both different those in the last cycle, the cycle time is represented by t.sub.c in the figure (generally about 150 ns), and the access time is represented by t.sub.CEA. Where only the column address is different from that in the last cycle, the cycle time is represented by t.sub.SC (about 50 ns), and the access time is represented by t.sub.CA. Accordingly, where the row address is the same as that in the last access cycle, an approach is employed to immediately read out data of a memory cell connected to the same word line already sensed from a bit line corresponding to the column address, thereby permitting the readout operation to be performed at a high speed.
However, in order to allowing the readout operation to be performed at a high speed in this way, it is necessary to change the CE signal as shown in dependency upon whether the row address changes or does not change. This requires an extra logic circuit. Further, it is necessary that the row address is latched at the fall time of the CE signal, and the column address is detected by the transition detector for a time period during which the CE signal is at L level. For this reason, it is required to discriminate which portion of the address corresponds to the row address on the system side. As a result, an employment of PSRAM in place of DRAM results in the problem that the merit that simplification can be made in medium and small systems is reduced.